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      "content": "Dang, this really is an issue in Yosys then. After updating Yosys to 0.64 I saw similar issues in the LibreLane CI: https://github.com/librelane/librelane/pull/916\nI dismissed them for now and didn't merge, hoping that the recent 0.65 release would rectify things, but it doesn't.\nIf you are able to create a Yosys-only reproducible, you could submit an issue upstream. If not, I'll try to create one tomorrow or simply explain the issue, perhaps someone has an idea what's going on.",
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          "title": "chore: update nix-eda to 6.16.0 by mole99 · Pull Request #916 · l...",
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          "description": "Updated nix-eda to 6.16.0\n\nUpdated Magic to 8.3.635\nUpdated Netgen to 1.5.318\nUpdated Yosys to 0.64\n\nUpdated yosys-eqy 0.64\nUpdated yosys-sby 0.64\nUpdated yosys-slang to 2026-03-25\nRemoved yosys-li...",
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      "content": "Changed the channel name: Yosys Issue",
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      "content": "The yosys version that the build is using is 0.64:\n` Yosys 0.64 (git sha1 d8dab5b32666564eca8e18f412973853ce006e61, clang++ 21.1.2 -fPIC -O3)`",
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      "content": "Or did you try it with 0.65 and that didn't fix it?",
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      "content": "I tried 0.65 with the LibreLane CI: https://github.com/fossi-foundation/nix-eda/pull/69",
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      "content": "I could also update the wafer.space branch to nix-eda with Yosys 0.65, but it probably wouldn't help :)",
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      "content": "Fair enough, I guess we need to roll back to 0.63 until it is fixed, and work out how to report the issue.\n\nIn config.yaml if I set the DESIGN_NAME to `uart_tx` and remove chip_top and chip_core I still get the issue, so that is getting towards a small repro.  But I'm not quite sure how to then wrap that up into something I can report to yosys",
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      "content": "Yes, I'll try overriding the Yosys version with 0.63 in the project template for now.\nI think LibreLane should be able to create a standalone reproducible, as it does for OpenROAD. Maybe pyosys complicates things, but we'll see.\nThe easiest way would be to write a small Yosys script that reads the Verilog and reproduces the issue, but I'm not sure it will be that easy :)",
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      "content": "In any case, thanks Mike, for giving this a try and identifying the issue!",
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      "content": "Ah - this may not be so hard to repro \uD83D\uDE04\n```\nyosys> read_verilog src/uart_tx.v\n\n1. Executing Verilog-2005 frontend: src/uart_tx.v\nParsing Verilog input from `src/uart_tx.v' to AST representation.\nGenerating RTLIL representation for module `\\uart_tx'.\nSuccessfully finished Verilog frontend.\n\nyosys> check\n\n2. Executing CHECK pass (checking for obvious problems).\nChecking module uart_tx...\nWarning: Wire uart_tx.\\next_fsm_state$func$src/uart_tx.v:128$1.tx_en is used but has no driver.\nWarning: Wire uart_tx.\\next_fsm_state$func$src/uart_tx.v:128$1.$result [3] is used but has no driver.\nWarning: Wire uart_tx.\\next_fsm_state$func$src/uart_tx.v:128$1.$result [2] is used but has no driver.\nWarning: Wire uart_tx.\\next_fsm_state$func$src/uart_tx.v:128$1.$result [1] is used but has no driver.\nWarning: Wire uart_tx.\\next_fsm_state$func$src/uart_tx.v:128$1.$result [0] is used but has no driver.\nFound and reported 5 problems.\n```",
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      "content": "I'll raise a yosys issue",
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      "content": "Awesome!",
      "author": {
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      "content": "https://github.com/YosysHQ/yosys/issues/5911",
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          "description": "Version Yosys 0.64 (git sha1 d8dab5b, clang++ 21.1.2 -fPIC -O3) On which OS did this happen? Linux Reproduction Steps Run yosys, read and check the verilog: yosys> read_verilog src/uart_tx.v yos...",
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      "content": "I tried to help them isolate by grabbing a couple of OSS CAD suite builds, it was present in a 0.63+ build, but not a 0.62+ (but I think OSS CAD suite might build off the dev branch so possibly the release 0.63 is ok)",
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      "content": "I've pushed an update to the project template that overrides Yosys with version 0.62: https://github.com/wafer-space/gf180mcu-project-template/pull/60/changes/9f23d7e3dad93aba1b9c8d15c748cc486014628a\nHowever, before merging the PR I hope that the issue will be fixed upstream.",
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      "content": "Well, something else fails with this older version. So we might just have to wait for a fix :)",
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      "content": "@Leo Moser (mole99) I see you got CI working on the PR now ?",
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      "content": "Yeah, it was already working before since the template does not trigger the regression in Yosys. When I backported Yosys to 0.62 something else broke, so I dropped that commit and am now waiting on a proper fix.",
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      "content": "Yosys 0.63 looks to be working for me - that might be worth a try",
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      "content": "@RebelMike Which versions of oss cad did you try  that was 0.63+?",
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      "content": "Ah hah, 20260307 fails",
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      "content": "So regression very early in dev after 0.63 release",
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      "content": "What's the reported hash ?",
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      "content": "Yosys 0.63+87 (git sha1 2f1cdc2df, clang++ 18.1.8 -fPIC -O3)",
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      "content": "```\ncommit e9442194f27140e3e80cb3bf407c3259d562c449\nAuthor: likeamahoney <likeamahoney@gmail.com>\nDate:   Fri Feb 27 20:42:40 2026 +0300\n\n    support automatic lifetime qualifier on procedural variables\n```",
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      "content": "this sounds like a possible culprit ?",
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      "content": "```\n0.62+119        04113eb95       bad     20260304\n0.62+117        1d3f9b790       works   20260302\n```",
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      "content": "@Leo Moser (mole99) You coul dtry reverting that",
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      "content": "Confirmed. I reverted this on `master` and that fixed the issue.",
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      "content": "Thank you!  Hopefully Leo can confirm if reverting that fixes the various other failures that Librelane CI picked up: https://github.com/librelane/librelane/actions/runs/26505823629",
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          "title": "chore: update nix-eda · librelane/librelane@3dec125",
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      "content": "Thanks for pinpointing the faulty commit!",
      "author": {
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      "content": "Let's see if this works:\n\n- https://github.com/fossi-foundation/nix-eda/pull/70\n- https://github.com/librelane/librelane/pull/916\n\nI also noticed a slight fmax regression as well, so I'll have to adjust the target frequency for some designs. But what can you do...",
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      "content": "Not done yet, but looking so far ...",
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      "content": "It seems that does the trick. Had to fix `CLOCK_PERIOD` slightly for two designs. `full_chip_sky130` now has issues which are likely due to a magic update, but I think those are valid issues. Looking into it.",
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      "content": "If this runs through I can properly rebase everything and finally update nix-eda in LibreLane again.\n\nhttps://github.com/librelane/librelane/pull/916/changes/d867039ca70d301a784f5b65e206076372d635b0",
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      "content": "The issue with `full_chip_sky130` was in the power ports. The sky130 pads have a separate port for the bondpad. But LibreLane would short all of the global connections for it. Until now I somehow managed to convince magic to short them during extraction as well. Not sure if this was actually buggy behavior or not? With a recent magic update this does not work anymore, so I've properly implemented power/ground busses in LibreLane.",
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